Faculty of Computer Science (Fredericton)

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Generating realistic trace files for memory management simulators by instrumenting IBM's J9 Java Virtual Machine
Generating realistic trace files for memory management simulators by instrumenting IBM's J9 Java Virtual Machine
by Johannes Ilisei, High-level programming languages like Java, C#, or Python rely on memory management systems that allocate and free objects automatically. A Java Virtual Machine (JVM) is responsible to execute compiled Java code. Several JVM implementations are available that include ongoing improvements throughout many years with reductions in execution time and memory footprint as well as the addition of new features. JVM implementations are large-sized projects that consist of many files, classes, and functions. Changing or extending the code can be a difficult and time consuming task. Therefore, simulators that reproduce desired JVM operations are available. They can be used to implement and test new features in little time. As with the Java Virtual Machine, a simulator requires instructions as form of input files with information on what operations to perform. These files are called trace files and they are generated with an instrumented JVM. Relevant operations are captured and printed into a file while running the JVM. This master's thesis focuses on the generation of trace files that represent JVM operations as realistically as possible. At the start of this project, two types of trace file generators already exist. Unfortunately, both of them contain errors that lead to a false JVM representation. Thereby, results gathered from simulators are unreliable. A new form of trace file generation is required that is able to produce correct inputs for a simulator. The project presented in this thesis captures JVM operations directly from IBM's J9 Java Virtual Machine's bytecode instructions. In addition, a comparison between previous and new trace files and their different effects on the simulator is part of this thesis., M.C.S. University of New Brunswick, Faculty of Computer Science, 2017.
Grailog KS Viz 2.0: graph-logic knowledge visualization by XML-based translation
Grailog KS Viz 2.0: graph-logic knowledge visualization by XML-based translation
by Leah Bidlake, Knowledge visualization is the expression of knowledge through graphical presentations with the goal of validating or communicating knowledge. Formal knowledge, which is used in Data Modeling, the Semantic Web, etc., is based on ontologies and rules, which can be represented in (Description and Horn) logics and presented as (generalized) graphs. Graph Inscribed Logic (Grailog) can be used to visualize RuleML knowledge. The earlier Grailog KS Viz transforms Datalog RuleML to Grailog visualizations in Scalable Vector Graphics (SVG). This thesis develops a tool, Grailog KS Viz 2.0, that is able to visualize Horn Logic (Hornlog) with Equality. It uses XSLT 2.0 with internal JavaScript to process arbitrary levels of function nesting in a recursive manner. The tool has also been extended from n-ary relations with n ≥ 2 to those with n ≥ 1 (including classes as unary relations), based on the labelnode normal form of Grailog. JavaScript is used to calculate the coordinates for positioning, and determines the dimensions of, the SVG elements and viewport, but is no longer required in the static image. Our Purifier thus removes the internal JavaScript from the static Grailog/SVG visualization generated by the tool. This assures that there are no malicious scripts, reduces the time required to render the Grailog/SVG visualization, and greatly reduces the final file size. The visualization of function applications with multiple levels of nesting generated by Grailog KS Viz 2.0 was evaluated using test cases that illuminate knowledge about graph-theoretical definitions. A larger use case was developed for teaching the business rules of managing the financial aspect of a non-profit organization. The processing speed as well as quality and accuracy of the rendered SVG are consistently high across common modern Web browsers. Grailog KS Viz 2.0 thus provides increased security, expressivity, and efficiency for viewing, sharing, and storing Grailog/SVG visualizations.
Graph-based IoT malware family classification
Graph-based IoT malware family classification
by Nastaran Mahmoudyar, Internet of Things malware has become one of the main cyber-threats nowadays. There is no comprehensive study in a feature-based manner for IoT malware detection approaches to the best of our knowledge. Moreover, the studies show that there is a lack of IoT malware family classification system. This thesis attempts to bridge these gaps by proposing a feature-based IoT malware taxonomy and a graph-based IoT malware family classification framework by combining the FCGs and fuzzy hashes. We introduce the Aggregated Weighted Graph (AWGH) of Hashes, representing each IoT malware family's structure. We use IDA Pro [60] for generating the FCGs, ssdeep [3] for computing the fuzzy hashes, and Python for developing the fully automated framework. To evaluate the system's effectiveness, we use the VirusTotal dataset [4] and provide a comparative analysis with different IoT malware regarding their CPU architectures (MIPS, ARM, i386, PowerPC, and AMD64). The results show the effectiveness of our framework.
High performance Python through workload acceleration with OMR JitBuilder
High performance Python through workload acceleration with OMR JitBuilder
by Dayton J. Allen, Python remains one of the most popular programming languages in many domains including scientific computing. Its reference implementation, CPython, is by far the most used version. CPython's runtime is bytecode-interpreted and leaves much to be desired when it comes to performance. Several attempts have been made to improve CPython's performance such as reimplementing performance-critical code in a more high-performance language (e.g. C, C++, Rust), or, transpiling Python source code to a more high-performance language, which is then called from within CPython through some form of FFI mechanism. Another approach is to JIT compile performance-critical Python methods or utilize alternate implementations that include a JIT compiler. JitBuilder provides a simplified interface to the underlying compiler technology available in Eclipse OMR. We propose using JitBuilder to accelerate performance-critical workloads in Python. By creating Python bindings to JitBuilder's public interface, we can generate native code callable from within CPython without any modifications to its runtime. Results demonstrate that our approach rivals and in many cases outperforms state-of-the-art JIT compiler based approaches in the current ecosystem { namely, Numba and PyPy.
High-level synthesis improvements and optimizations in Odin II
High-level synthesis improvements and optimizations in Odin II
by Bo Yan, A Field-Programmable Gate Array (FPGA) is an integrated circuit that allows users to program product features and functions after manufacturing. Verilog-to-Routing (VTR) is an open source CAD tool for conducting FPGA architecture and CAD research. As one of the core tools of VTR, Odin II is responsible for Verilog elaboration and hard block synthesis. This project describes the improvements in Odin II on three aspects: for loop support, AST simplication and hard block reduction. A for loop is an important statement in Verilog HDL and should be supported by Odin II. There are different entry points to simplify an AST, and this thesis demonstrates three ways for this purpose: simplifying expressions with variables, reducing parameters with values and using shift operations when possible to replace multiplication or division. For the needs of the Verilog code, some hard blocks in the netlist have the same high-level function. This project provides a method to reduce redundant hard blocks. Each implementation is tested by designed test cases or sets of standard benchmarks, and the results of running them through Odin II and VTR are shown. From the results, improvements are demonstrated., Electronic Only. (UNB thesis number) Thesis 9518. (OCoLC) 965908870., M.C.S., University of New Brunswick, Faculty of Computer Science, 2014.
Holovision: asynchronous mixed reality groupware to support physical work tasks
Holovision: asynchronous mixed reality groupware to support physical work tasks
by Alexander William Kienzle, Software that supports collaboration (groupware) is becoming ubiquitous in the workplace. The ability to share documents, images, and videos, or to have face-to-face conversations almost anywhere and anytime has transformed the workplace and increased productivity. At the same time, mixed reality devices are beginning to gain traction as viable platforms to support the production and consumption of new forms of information like spatial data and in-situ 3D objects. Current groupware systems focus largely on supporting virtual work, that is information work and manipulating information that can be displayed on the screen. However, many work tasks are physical in nature, they require manipulating, repairing, and assembling physical objects. The ability to share these new forms of information offers new and relatively under explored opportunities for collaboration around physical work tasks. Drawing on inspiration from previous research in the field, as well as 3D guidance techniques in video games, the mixed reality groupware system, “HoloVision” was created to take advantage of this new collaboration medium and provide a proof-of-concept for the design of future asynchronous mixed reality groupware systems. In this thesis, I document the background research, design, development, and testing of HoloVision as a novel mixed reality groupware system that combines speech-to-text, gaze, video, and spatial data, in a way that allows a user to intuitively author persistent “hypermedia” annotations to asynchronously support the guidance of future users in both collocated and remote workspaces.
How the visual design of video game antagonists affects perception of morality
How the visual design of video game antagonists affects perception of morality
by Reyhan Pradantyo, Antagonists play an important role in video games, as they often act as the source of a game's main challenge. A key part of how antagonists are experienced is through their visual design. Antagonists differ from other characters in that they are typically viewed as being immoral. However, there is limited research focused specifically on how antagonists are visually designed, and how this affects players' perceptions of antagonist morality. To build this understanding, we gathered people's ratings of 105 antagonists. By examining the correlation between the prominence of antagonists' visual attributes and how “bad” participants perceive a character, our findings provide new insight into the design of characters. We also show how the antagonist designs in our sample show a spectrum of morality and are not always perceived as purely or clearly immoral. We provide an improved understanding of game design practices and explore how they can be better studied and supported.
ILP models for scheduling while minimizing peak power consumption
ILP models for scheduling while minimizing peak power consumption
by Damian Jewett, The Peak Power Minimization Scheduling Problem (PPMSP) is a job shop scheduling problem where peak power consumption is minimized, as opposed to makespan, total cost or some other common objective. A formal integer linear programming (ILP) model is developed for this scheduling problem, called the initial PPMSP model. This initial model is then used to create the Scheduler, an application for creating production schedules given unscheduled sets of production data constrained under precedence relations. The Scheduler uses a free solver called GLPSOL. The Estimator is another application that, given a production schedule, generates a plot of the expected power consumption over the course of the schedule. Later, an alternate PPMSP model is discussed, which aims to improve solution times by using fewer binary variables. Testing indicates that the alternate model provides no significant improvement in practice. Much better solution times can be achieved with more powerful solvers, such as CPLEX., Electronic Only. (UNB thesis number) Thesis 9455. (OCoLC)956660240., M.C.S. University of New Brunswick, Faculty of Computer Science, 2014.
Implementing a content-based recommender system for news readers
Implementing a content-based recommender system for news readers
by Mahta Moattari, Recommender systems are widely used to suggest items to users based on users' interests. Content-based recommender systems are popular, specifically in the area of news services. This report describes the implementation of an effective online news recommender system by combining two different algorithms. Our first algorithm employs users' activity histories as inputs. Then it processes this data using a Bayesian framework to predict users' genuine interests[10], and as a result suggests new articles based on those interests. The other algorithm attempts to find keyword matches among the user's keywords and new articles' keywords to suggest new articles to that user. The Java language was used to implement these algorithms. To test the system, ten different users were chosen randomly among those users who posted comments for more than 50 articles from 2012/05/01 to 2012/07/30. These experiments show that our system successfully suggested new articles to users based on their fields of interest., A Report Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Computer Science in the Graduate Academic Unit of Computer Science Electronic Only. (UNB thesis number) Thesis 9192. (OCoLC) 960905592, M.C.S., University of New Brunswick, Faculty of Computer Science, 2013.
Improved ordering of ESOP cubes for Toffoli networks
Improved ordering of ESOP cubes for Toffoli networks
by Zakaria Hamza, Logic synthesis deals with the problem of finding a cost-effective realization of a given logic function. This uses several state-of-the-art techniques and involves several tools of mathematical origin. In recent years reversible logic has been suggested to address the power consumption associated with computation. To accomplish such a task, synthesis of reversible logic function is needed. Several new synthesis methods have been developed. In this thesis methods are proposed that improve on a given synthesis method. In particular, interest has been demonstrated in the optimization of this class of circuits which use the particular Exclusive-or Sum of Product (ESOP) terms representation. The advantage this representation format offers is in the ease of mapping the function to a network of Toffoli logic gates. However, this synthesis technique provides non-optimal results which could be improved. This problem has roots in both the representation and mapping processes of synthesis. It is well-known that the order of the terms in the ESOP expression will have a direct effect on the cost of the implementation. The problem of finding the optimal order can be mapped into the Generalized Traveling Salesman Problem. Another route of optimization involves reducing the number of terms used to represent the function. This can be achieved by canonical representation of functions. Both of these have proven to offer enhancements over existing synthesis techniques and have been developed in this thesis. Experimental results show that significant improvements can be achieved with the proposed methods., (UNB thesis number) Thesis 8777. (OCoLC)810261535., M.C.S. University of New Brunswick, Faculty of Computer Science, 2011
Improving PySpark performance with cross-language optimization
Improving PySpark performance with cross-language optimization
by Linh-Nga Tran, Big data is a rapidly growing field, and Apache Spark is one of the most commonly used frameworks in this area. Among its APIs, Spark for Python, or PySpark is usually the preferred choice by the data scientist community due to its simplicity and versatility. PySpark is built upon Java Spark, and operates in two runtimes, Python and Java Virtual Machine. However, PySpark is often outperformed by its alternatives in various applications. From previous experiments, the bottleneck in PySpark is identified as the data marshalling process across the language boundary between Python and Java, specifically in the serialization and deserialization process. This project aims to alleviate this issue by implementing a specialized serializer for PySpark. The specialized serializer is first built in C++. In addition, to allow for the serialization and deserialization code to be generated dynamically depending on the schema of the dataset, Just-in-Time (JIT) technology is utilized. To be more specific, OMR JitBuilder is used to compile the code at runtime depending on user input. Furthermore, the compiled code can then be assigned to normal functions and be re-used multiple times, hence saving compilation and binding effort. After building the serializer in C++, the wrappers for Python and Java are implemented. On the Python side, to transfer data between C++ and the source language, ctypes and a header file from the Python development package, Python.h, are used. The ctypes library allows communication from Python to C++, and the header file enables C++ to access and modify Python objects. On the Java side, Java Native Interface, a tool for Java to pass data and make native calls, is used. This JitBuilder serializer is then evaluated against other existing serializers, in particular pickle, BSON, and Protocol Buffers. The dataset used is the Part table from the TPC-H benchmark, and it has scale factors of 1, 2, 4, and 8, corresponding to 24.1, 48.4, 96.9, and 194.4 MB. The serializers are tested in different scenarios, which are serialization and deserialization only in the Python runtime, serialization and deserialization only in the JVM, and finally serialization in one language and deserialization of that data in the other language. The results show that this serializer has competitive performance, and in some cases outperforms the other options. After implementing and evaluating the JitBuilder serializer with the wrappers for Python and Java, a prototype is built where it is integrated into PySpark. To do this, the function calls to serialize and deserialize data in Spark source code are modified. This modified PySpark is shown to have better performance than the original PySpark in common data applications.
Improving memory and validation support in FPGA architecture exploration
Improving memory and validation support in FPGA architecture exploration
by Andrew Somerville, The Verilog-to-Routing (VTR) computer aided design (CAD) flow provides researchers with a unique ability: to explore the properties of hypothetical field-programmable gate array (FPGA) architectures and to explore various improvements to different stages of the CAD flow. This work enhances the VTR CAD flow first by providing a high performance verification framework, as well as a verification of the elaboration stage of the CAD flow. The CAD flow is also extended to support the elaboration and exploration of soft logic memories as well as more flexible hard block memory splitting and padding. Experimental results show that these new capabilities are useful in architecture exploration. Results also show that small soft logic memories can provide superior area efficiency and critical path delay on homogenous memory architectures containing only large block memories., Electronic only. (UNB thesis number) Thesis 9249. (OCoLC) 961102423., M.C.S., University of New Brunswick, Faculty of Computer Science, 2013.

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