Visual exploration of changing FPGA architectures in the VTR project

Abstract

Field Programmable Gate Arrays (FPGA) are used for prototyping hardware as well as in applications with frequently changing requirements. Boolean circuits produced based on hardware description language files are created by a Computer Aided Design (CAD) flow in order to optimize applications for a specific architecture. The Verilog to Routing (VTR) project provides an FPG A CAD flow developed especially for academic and experimental purposes. The CAD flow consists of the tools Odin II, ABC and VPR. This project describes the development of a visualization component capable of showing the netlist produced and optimized by the CAD flow. The ability to simulate the shown circuit not only allows developers to explore the structure of a circuit, but also to verify its functionality. The visualization is part of Odin II and uses its abilities such as the Odin II file handling and simulation. The application aims to assist developers in exploring how a netlist changes during the work flow. The improvement of Odin II and its simulation component is part of the thesis. In addition the ability to elaborate and simulate circuits with multiple clocks was added to the tool and the functionality embedded into the visualization component. Using the new abilities of Odin II in combination with the flexibility of other tools in the VTR CAD flow new FPGA architectures can be evaluated and tested. Designs which utilize multiple clocks in combination with hard logic can be elaborated, simulated and verified. The visual component provides functionalities to assist the process as netlists generated by Odin II and optimized by later stages in the CAD flow can be explored visually. This includes a visual simulation as well as the exploration of activity estimation data. The improvements aim to assist in research and experimentation with new FPGA architectures which could benefit research and industry.