Design and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array

Landry, Jacques2023-06-072023-06-071997https://unbscholar.lib.unb.ca/handle/1882/34796en-CAhttp://purl.org/coar/access_right/c_16ecDesign and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate arraysenior reportM., LukeEngineering