Browsing by Author "Nasartschuk, Konstantin"

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    Improving virtual machines using string deduplication and internal object pools
    (University of New Brunswick, 2019) Nasartschuk, Konstantin; Kent, Kenneth
    The efficiency of memory management is one of the key metrics when researching virtual machines. In cases where deallocation of objects is performed automatically, garbage collection has become an important field of research. It aims at speeding up and optimizing the execution of applications written in languages such as Java, C#, Python and others. Even though garbage collection techniques have become more sophisticated, automatic memory management is still far from being optimal. Garbage collection techniques such as mark sweep, mark compact, copying collection, and generational garbage collection form the base of most virtual environments. These algorithms rely on a stop-the-world phase that is used to detect and free live objects. The research presented in this dissertation aims at improving automatic memory management by investigating the optimization of memory layout as well as optimizing the allocation and deallocation processes of frequently created and freed objects. The first optimization aims at using the stop-the-world phase of the garbage collector in order to detect duplicate strings and deduplicate them before copying them to a new region. The goal of this algorithm is to reduce multiple storage of the same data in memory, as well as copying of memory, in order to decrease the heap size and therefore the number of garbage collections required to execute the client application. The second optimization aims at speeding up the allocation of frequently created and discarded objects by keeping a pool of empty objects. Instead of requesting new memory, the virtual machine requests an empty object of the class and initializes the values required. Object pools are a widely used software engineering pattern utilized by software developers to reuse object instances without the need of repeated allocation and instantiation. While the benefits of using object pool structures are still present when used in a garbage collected environment, it adds a memory management component to the development process. The dissertation investigates the feasibility of introducing automatically created and maintained object pools for predefined classes. Automatic object pools are implemented and discussed using the GenCon GC and Balanced GC policies of the IBM Java VM.
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    Visual exploration of changing FPGA architectures in the VTR project
    (University of New Brunswick, 2013) Nasartschuk, Konstantin; Kent, Kenneth; Herpers, Rainer
    Field Programmable Gate Arrays (FPGA) are used for prototyping hardware as well as in applications with frequently changing requirements. Boolean circuits produced based on hardware description language files are created by a Computer Aided Design (CAD) flow in order to optimize applications for a specific architecture. The Verilog to Routing (VTR) project provides an FPG A CAD flow developed especially for academic and experimental purposes. The CAD flow consists of the tools Odin II, ABC and VPR. This project describes the development of a visualization component capable of showing the netlist produced and optimized by the CAD flow. The ability to simulate the shown circuit not only allows developers to explore the structure of a circuit, but also to verify its functionality. The visualization is part of Odin II and uses its abilities such as the Odin II file handling and simulation. The application aims to assist developers in exploring how a netlist changes during the work flow. The improvement of Odin II and its simulation component is part of the thesis. In addition the ability to elaborate and simulate circuits with multiple clocks was added to the tool and the functionality embedded into the visualization component. Using the new abilities of Odin II in combination with the flexibility of other tools in the VTR CAD flow new FPGA architectures can be evaluated and tested. Designs which utilize multiple clocks in combination with hard logic can be elaborated, simulated and verified. The visual component provides functionalities to assist the process as netlists generated by Odin II and optimized by later stages in the CAD flow can be explored visually. This includes a visual simulation as well as the exploration of activity estimation data. The improvements aim to assist in research and experimentation with new FPGA architectures which could benefit research and industry.