Creation of a VHDL behavioral model for a LSI/VLSI chip

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dc.contributor.advisorM., Luke
dc.contributor.authorWen, Ling Liang
dc.date.accessioned2023-06-07T18:19:07Z
dc.date.available2023-06-07T18:19:07Z
dc.date.issued1992
dc.description.copyrightNot available for use outside of the University of New Brunswick
dc.description.noteWen, Ling Liang (1992). Creation of a VHDL behavioral model for a LSI/VLSI chip . (Engineering Senior Report no. EE-290 1992). Fredericton : University of New Brunswick, Dept. of Electrical and Computer Engineering EE-290 1992 1882/16317
dc.format.mediumelectronic
dc.identifier.urihttps://unbscholar.lib.unb.ca/handle/1882/31643
dc.language.isoen_CA
dc.publisherUniversity of New Brunswick
dc.rightshttp://purl.org/coar/access_right/c_16ec
dc.subject.disciplineEngineering
dc.titleCreation of a VHDL behavioral model for a LSI/VLSI chip
dc.typesenior report
thesis.degree.disciplineEngineering
thesis.degree.fullnameBachelor of Science in Engineering
thesis.degree.grantorUniversity of New Brunswick
thesis.degree.levelundergraduate
thesis.degree.nameBachelor of Science in Engineering

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