Browsing by Author "Khadivi, Daniel"

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    Parmys: Odin-II intelligent partial mapper for Yosys synthesis suite
    (University of New Brunswick, 2023-08) Khadivi, Daniel; Kent, Kenneth B.
    Partial mapping is to preallocate design logic at the beginning stages of the synthesis flow. Verilog-to-Routing (VTR) is an open-source FPGA architecture research framework. Odin-II provides Verilog elaboration and partial mapping for the VTR flow. Yosys is a Register-Transfer-Level (RTL) synthesis framework with extensive Verilog-2005 support. Partial mapping is possible in Yosys, but users are forced to manually determine the circuit implementation. Parmys automates the hard logic inference and the hard or soft mapping decisions for Yosys through the Odin-II intelligent partial mapper and brings architectural awareness to Yosys. This thesis discusses steps taken to add the Odin-II partial mapper into Yosys. Parmys expands research opportunities for Yosys users in the area of partial mapping considering FPGA architecture and device capacity. The standard VTR benchmarks showed improvement for all key quality-of-result (QoR) metrics when using the Parmys plug-in with the Yosys elaborator as the frontend in the VTR flow.