Improving memory and validation support in FPGA architecture exploration

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dc.contributor.advisorKent, Kenneth
dc.contributor.authorSomerville, Andrew
dc.date.accessioned2023-03-01T16:20:50Z
dc.date.available2023-03-01T16:20:50Z
dc.date.issued2013
dc.date.updated2016-10-24T00:00:00Z
dc.description.abstractThe Verilog-to-Routing (VTR) computer aided design (CAD) flow provides researchers with a unique ability: to explore the properties of hypothetical field-programmable gate array (FPGA) architectures and to explore various improvements to different stages of the CAD flow. This work enhances the VTR CAD flow first by providing a high performance verification framework, as well as a verification of the elaboration stage of the CAD flow. The CAD flow is also extended to support the elaboration and exploration of soft logic memories as well as more flexible hard block memory splitting and padding. Experimental results show that these new capabilities are useful in architecture exploration. Results also show that small soft logic memories can provide superior area efficiency and critical path delay on homogenous memory architectures containing only large block memories.
dc.description.copyright© Andrew Somerville, 2013
dc.description.noteElectronic only. (UNB thesis number) Thesis 9249. (OCoLC) 961102423.
dc.description.noteM.C.S., University of New Brunswick, Faculty of Computer Science, 2013.
dc.formattext/xml
dc.format.extentx, 66 pages
dc.format.mediumelectronic
dc.identifier.oclc(OCoLC) 961102423
dc.identifier.otherThesis 9249.
dc.identifier.urihttps://unbscholar.lib.unb.ca/handle/1882/13592
dc.language.isoen_CA
dc.publisherUniversity of New Brunswick
dc.rightshttp://purl.org/coar/access_right/c_abf2
dc.subject.disciplineComputer Science
dc.subject.lcshVerilog (Computer hardware description language)
dc.subject.lcshComputer-aided design.
dc.subject.lcshField programmable gate arrays.
dc.titleImproving memory and validation support in FPGA architecture exploration
dc.typemaster thesis
thesis.degree.disciplineComputer Science
thesis.degree.fullnameMaster of Computer Science
thesis.degree.grantorUniversity of New Brunswick
thesis.degree.levelmasters
thesis.degree.nameM.C.S.

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