High-level synthesis improvements and optimizations in Odin II
University of New Brunswick
A Field-Programmable Gate Array (FPGA) is an integrated circuit that allows users to program product features and functions after manufacturing. Verilog-to-Routing (VTR) is an open source CAD tool for conducting FPGA architecture and CAD research. As one of the core tools of VTR, Odin II is responsible for Verilog elaboration and hard block synthesis. This project describes the improvements in Odin II on three aspects: for loop support, AST simplication and hard block reduction. A for loop is an important statement in Verilog HDL and should be supported by Odin II. There are different entry points to simplify an AST, and this thesis demonstrates three ways for this purpose: simplifying expressions with variables, reducing parameters with values and using shift operations when possible to replace multiplication or division. For the needs of the Verilog code, some hard blocks in the netlist have the same high-level function. This project provides a method to reduce redundant hard blocks. Each implementation is tested by designed test cases or sets of standard benchmarks, and the results of running them through Odin II and VTR are shown. From the results, improvements are demonstrated.