The improvement of the VTR project by using carry-chains and power specification
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Date
2013
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University of New Brunswick
Abstract
A Field-Programmable Gate Array (FGPA) is a type of logic chip that can be
programmed after manufacturing. It is especially popular for prototyping integrated
circuit designs. The Verilog-To-Routing flow is an open source CAD
tool for researchers to explore different properties of hypothetical FPGA architecture.
As a part of the VTR project, ODIN_II reads a Verilog file as
well as an architecture file, elaborates and synthesis, to produce a BLIF file
for later usage. This work enhances the VTR flow first by supporting carry
chains. This requires elaboration and exploration of hard block adders during
the whole CAD flow. The CAD flow is also extended by adding parameter
syntax support and introducing power specification. A power specification
file is processed into an equivalent power specification BLIF file. Experiments
on carry chains prove that hard block adders are better to use for large-sized
additions. Results also show soft adders can provide less critical path delay
and area efficiency on Island-Style FPGAs.