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Design and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array
Design and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array
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Date
1997
Authors
Landry, Jacques
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University of New Brunswick
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https://unbscholar.lib.unb.ca/handle/1882/34796
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