Design and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array

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dc.contributor.advisorM., Luke
dc.contributor.authorLandry, Jacques
dc.date.accessioned2023-06-07T20:38:09Z
dc.date.available2023-06-07T20:38:09Z
dc.date.issued1997
dc.description.copyrightNot available for use outside of the University of New Brunswick
dc.description.noteLandry, Jacques (1997). Design and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array . (Engineering Senior Report no. EE-499 1997). Fredericton : University of New Brunswick, Dept. of Electrical and Computer Engineering EE-499 1997 1882/12463
dc.identifier.urihttps://unbscholar.lib.unb.ca/handle/1882/34796
dc.language.isoen_CA
dc.publisherUniversity of New Brunswick
dc.rightshttp://purl.org/coar/access_right/c_16ec
dc.subject.disciplineEngineering
dc.titleDesign and development of a verilog model to capture the programmable throttle and latency function using a field programmable gate array
dc.typesenior report
thesis.degree.disciplineEngineering
thesis.degree.fullnameBachelor of Science in Engineering
thesis.degree.grantorUniversity of New Brunswick
thesis.degree.levelundergraduate
thesis.degree.nameBachelor of Science in Engineering

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