Investigating FPGA architectures for System-on-Chip
| dc.contributor.advisor | Kent, Kenneth | |
| dc.contributor.author | Li, Jingjing | |
| dc.date.accessioned | 2023-03-01T16:43:37Z | |
| dc.date.available | 2023-03-01T16:43:37Z | |
| dc.date.issued | 2014 | |
| dc.date.updated | 2023-03-01T15:03:10Z | |
| dc.description.abstract | This work describes the development of a System-on-Chip processor in the VTR flow and the investigation of a better FPG A architecture for a SoC processor. ODIN II, as a part of the VTR workflow, is modified to support the simulation of a SoC processor. In addition, the ability to support external logic memories was extended to the tool. The external memories are processed in a MIF file. The FPGA architecture specification file, as an input of the VTR workflow, requires exploration with different hard blocks, such as HB Memories, HB Adders and HB Multipliers. Experiments on simulating the SoC processor in the VTR flow for FPGAs show that an FPGA architecture with hard block (HB) Memories, 2-bit HB Adders and 36*36 HB Multipliers is better than other FPGA architectures for an ARM Core processor. The exploration of this work is also on supporting multiple SoC processors on FPGAs. | |
| dc.description.copyright | © Jingjing Li, 2014 | |
| dc.format | text/xml | |
| dc.format.extent | ix, 101 pages | |
| dc.format.medium | electronic | |
| dc.identifier.uri | https://unbscholar.lib.unb.ca/handle/1882/14391 | |
| dc.language.iso | en_CA | |
| dc.publisher | University of New Brunswick | |
| dc.rights | http://purl.org/coar/access_right/c_abf2 | |
| dc.subject.discipline | Computer Science | |
| dc.title | Investigating FPGA architectures for System-on-Chip | |
| dc.type | master thesis | |
| thesis.degree.discipline | Computer Science | |
| thesis.degree.fullname | Master of Computer Science | |
| thesis.degree.grantor | University of New Brunswick | |
| thesis.degree.level | masters | |
| thesis.degree.name | M.C.S. |
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