Yosys+Odin-II: The Odin-II partial mapper with Yosys coarse-grained netlists in VTR
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Date
2021-11
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University of New Brunswick
Abstract
Verilog-to-routing (VTR) provides users with an entire flow from the Verilog circuit description to a final FPGA programming configuration. The VTR front-end interface for Verilog compilation, Odin-II, lacks support for the Verilog-2005 standard and SystemVerilog. However, Odin-II provides complex partial mapping for balancing soft logic and hard blocks such as embedded multipliers, adders, and memories in FPGA architectures. Yosys, an open framework for Register Transfer Level (RTL) synthesis, provides extensive support for HDLs. However, the Yosys flow forces the user to decide the discrete circuit implementation manually. The approach taken by Yosys is to map all discrete components into available hard blocks or to explode them in low-level logic when not available. This thesis proposes improving device utilization and simplifying the flow by automating hard logic decisions with architecture awareness. Yosys, as a front-end HDL elaborator, in combination with the Odin-II partial mapper, is added to the VTR flow.