Generating realistic trace files for memory management simulators by instrumenting IBM's J9 Java Virtual Machine

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dc.contributor.advisorKent, Kenneth
dc.contributor.advisorDueck, Gerhard
dc.contributor.authorIlisei, Johannes
dc.date.accessioned2023-03-01T16:27:47Z
dc.date.available2023-03-01T16:27:47Z
dc.date.issued2017
dc.date.updated2019-03-04T00:00:00Z
dc.description.abstractHigh-level programming languages like Java, C#, or Python rely on memory management systems that allocate and free objects automatically. A Java Virtual Machine (JVM) is responsible to execute compiled Java code. Several JVM implementations are available that include ongoing improvements throughout many years with reductions in execution time and memory footprint as well as the addition of new features. JVM implementations are large-sized projects that consist of many files, classes, and functions. Changing or extending the code can be a difficult and time consuming task. Therefore, simulators that reproduce desired JVM operations are available. They can be used to implement and test new features in little time. As with the Java Virtual Machine, a simulator requires instructions as form of input files with information on what operations to perform. These files are called trace files and they are generated with an instrumented JVM. Relevant operations are captured and printed into a file while running the JVM. This master's thesis focuses on the generation of trace files that represent JVM operations as realistically as possible. At the start of this project, two types of trace file generators already exist. Unfortunately, both of them contain errors that lead to a false JVM representation. Thereby, results gathered from simulators are unreliable. A new form of trace file generation is required that is able to produce correct inputs for a simulator. The project presented in this thesis captures JVM operations directly from IBM's J9 Java Virtual Machine's bytecode instructions. In addition, a comparison between previous and new trace files and their different effects on the simulator is part of this thesis.
dc.description.copyright© Johannes Ilisei, 2017
dc.description.noteM.C.S. University of New Brunswick, Faculty of Computer Science, 2017.
dc.formattext/xml
dc.format.extentxi, 93 pages
dc.format.mediumelectronic
dc.identifier.otherThesis 10004
dc.identifier.urihttps://unbscholar.lib.unb.ca/handle/1882/13898
dc.language.isoen_CA
dc.publisherUniversity of New Brunswick
dc.rightshttp://purl.org/coar/access_right/c_abf2
dc.subject.classificationTrace file generators.
dc.subject.classificationMemory management simulators.
dc.subject.disciplineComputer Science
dc.subject.lcshJava virtual machine -- Computer simulation.
dc.subject.lcshVirtual computer systems -- Computer simulation.
dc.subject.lcshSoftware frameworks.
dc.subject.lcshComputer software -- Development.
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshGarbage collection (Computer science)
dc.subject.lcshGenerators (Computer programs)
dc.subject.lcshJava (Computer program language)
dc.titleGenerating realistic trace files for memory management simulators by instrumenting IBM's J9 Java Virtual Machine
dc.typemaster thesis
thesis.degree.disciplineComputer Science
thesis.degree.fullnameMaster of Computer Science
thesis.degree.grantorUniversity of New Brunswick
thesis.degree.levelmasters
thesis.degree.nameM.C.S.

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