Advancing VTR flow: Integrating ABC9 via Yosys for enhanced technology mapping and optimization
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Date
2024-06
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University of New Brunswick
Abstract
This thesis delves into optimizing the Verilog-to-Routing (VTR) flow, which is crucial in open-source Computer-Aided Design and Field-Programmable Gate Array (FPGA) architecture research. It utilizes ODIN II and Parmys for synthesis, ABC for technology mapping, and Versatile Place and Route for packing, placement, and routing. ABC9 optimizations are implemented as a pass within the Yosys Open SYnthesis Suite, which is utilized in the Parmys front-end, besides the partial mapper of ODIN II. Integrating the ABC9 pass enhances technology mapping and optimizations in the VTR workflow, surpassing the conventional ABC tool and improving results for large and complex designs. The ABC9 pass optimizes timing behavior in complex multi-clock designs and incorporates a delay model for hard blocks in the target FPGA architecture. Various benchmarks evaluate the workflow’s efficacy across diverse designs, including small-scale and large-scale ones with hard blocks, soft logic, and digital signal processors (DSP). This ensures a comprehensive assessment across different complexities and FPGA utilization scenarios.