Improving memory and validation support in FPGA architecture exploration

Abstract

The Verilog-to-Routing (VTR) computer aided design (CAD) flow provides researchers with a unique ability: to explore the properties of hypothetical field-programmable gate array (FPGA) architectures and to explore various improvements to different stages of the CAD flow. This work enhances the VTR CAD flow first by providing a high performance verification framework, as well as a verification of the elaboration stage of the CAD flow. The CAD flow is also extended to support the elaboration and exploration of soft logic memories as well as more flexible hard block memory splitting and padding. Experimental results show that these new capabilities are useful in architecture exploration. Results also show that small soft logic memories can provide superior area efficiency and critical path delay on homogenous memory architectures containing only large block memories.