Investigating FPGA architectures for System-on-Chip
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Date
2014
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University of New Brunswick
Abstract
This work describes the development of a System-on-Chip processor in the
VTR flow and the investigation of a better FPG A architecture for a SoC
processor. ODIN II, as a part of the VTR workflow, is modified to support
the simulation of a SoC processor. In addition, the ability to support
external logic memories was extended to the tool. The external memories
are processed in a MIF file. The FPGA architecture specification file, as an
input of the VTR workflow, requires exploration with different hard blocks,
such as HB Memories, HB Adders and HB Multipliers. Experiments on simulating
the SoC processor in the VTR flow for FPGAs show that an FPGA
architecture with hard block (HB) Memories, 2-bit HB Adders and 36*36
HB Multipliers is better than other FPGA architectures for an ARM Core
processor. The exploration of this work is also on supporting multiple SoC
processors on FPGAs.